FIG. 1 depicts a traditional CPU complex 101 and system memory complex 102 for a multi-core processor 100. The processor or “host” side of the system memory complex 102 includes a memory controller 103 that interfaces with a system memory 104. As is understood in the art, the individual processing cores 101_1 through 101_N of a multi-core processor will snoop their internal caches (not shown) for the program and data needed by their respective threads. If an item of program code or data desired by a processing core thread is not found in the core's cache, the program code or data item may ultimately be fetched from system memory 104 by the memory controller 103.
The processing cores 101_1 through 101_N are interconnected by an interconnection network 105 (e.g., mesh network, front side bus, etc.) that is coupled to a last level cache 106. A last level cache 106, typically, caches program code and data for all the cores 101_1 through 101_N of the processor 100 rather than any particular core. A last level cache 106 is typically the last cache that is snooped for a desired item of program code or data before fetching the item from system memory 104 through the memory controller 103.
A system's performance may become inefficient if cacheable items are entered into a cache, such as the LLC 106, and then never called upon until eventually being evicted out the cache.